Static random-access memory (SRAM) is a common type of semiconductor memory that uses bi-stable latching circuitry to store each bit of binary data (e.g., “0” or “1”). SRAM does not require periodic refreshing to maintain its data if left undisturbed. However, it is typically still volatile in that data is lost when power is removed. A conventional SRAM is composed of an array of individual SRAM bit cells, where each bit cell stores a single bit of data accessed by a pair of complementary bit lines known as bit line true (BLT) and bit line complementary (BLC). Each bit cell is in turn composed of a number of transistors which together store the bit itself and control access to it.
Problems have arisen in maintaining the functional integrity of SRAM bit cells as semiconductor memory technology continues to scale to smaller sizes, greater densities, and lower power schemes. In particular, the read and write margins of SRAM bit cells, which relate to how reliably the bits of the SRAM cells can be read from and written to, are reduced as operating voltages are reduced with the down-scaling of circuit size. Reduced read and write margins may consequently cause errors with read and write operations of the SRAM cells.